BE-T1000 Microprocessor - Multicore System on Chip

Name: BE-T1000 Microprocessor - Multicore System on Chip
Brand: Baikal Electronics
Availability: InStock

Brand: Baikal Electronics

$60 - $300 USD

MOQ: 20 pieces

Key Features

Core: Two P-Class P5600 r5 cores running at 1.2 GHz

Power consumption: 5 cm³

Overall dimensions: 25?25 mm

Case: Housing HFCBGA-576. Dimensions: 25x25 mm (576 pins)

Supplier Information

BAIKAL ELECTRONICS OJSC

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Description

The BE-T1000 integrated circuit (originally named Baikal-T1) is the first microprocessor in the line of multi-core systems-on-chip (SOC) from Baikal Electronics. The BE-T1000 combines high computing performance with low power consumption.

The microprocessor is based on a dual-core system of MIPS32® P5600™ family with an operating frequency of 1.2 GHz, equipped with a wide range of high-speed interfaces PCIe Gen3, 10 Gb Ethernet, 1 Gb Ethernet, USB 2.0, SATA 6G and low-speed peripherals I 2C, SPI, UART, GPIO. The microprocessor is optimised for use in industrial automation, communication and networking equipment, as well as embedded systems for various purposes, can be used to create thin and zero clients, in recording and visualisation tools.

The BE-T1000 chip is manufactured using a 28-nanometre process technology. Its power consumption does not exceed 5W.

Specifications

Core

Two P-Class P5600 r5 cores running at 1.2 GHz

Power consumption

5 cm³

Overall dimensions

25?25 mm

Case

Housing HFCBGA-576. Dimensions: 25x25 mm (576 pins)

System monitoring

PVT контроллер; Сторожевой таймер

Low-speed interfaces

Programmable Watchdog Timer (WDT); 3 programmable 50MHz timers; GPIO interfaces: 32 bit and 3 bit; 2 UART interfaces; 2 SPI interfaces; 3 I2C controllers

High-speed interfaces

PCIe x4 Gen3 interface (4 paths with 8 Gb/s bandwidth each); USB 2.0 controller (ULPI); Two SATA 6G interfaces; 10 Gb Ethernet interface (10GBASE KX4, 10GBASE KR); 2 1 Gb Ethernet controllers (RGMII).

Main interconnect

Support AMBA 3 AXI protocol; 5 AXI channels; 40-bit address.

Memory interfaces

32-bit DDR3-1600 memory module interface with 8-bit error correction code; 40-bit application address; Supports up to 8GB external SDRAM memory modules

Technological process, nm

Processor system based on dual-core cluster

MIPS32 architecture; Two P-Class P5600 r5 cores running at 1.2 GHz; 128 KB L1 level cache (64 KB data cache and 64 KB instruction cache) in each core; 1 MB L2 level cache managed by the Coherence Manager controller; Compute

Operating temperature range

0...70 million m³