High performance digital signal processor. The processor architecture is based on the new generation of VLIW/SIMD processor core NMC4.
The processor contains two processor cores NMPU0 and NMPU1, each of which includes a RISC processor and a vector coprocessor. The first 64-bit coprocessor is designed to perform vector-matrix operations on integer data of variable length from 1 to 64 bits.
The second 64-bit coprocessor is designed for vector floating-point operations.
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